1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having layers formed by means of molecular beam epitaxy and a method of fabricating a semiconductor device by using an apparatus for carrying out molecular beam epitaxy.
2. Description of the Related Art
Japanese Unexamined Patent Publication No. 5-211158 has suggested a method of fabricating a semiconductor device by means of molecular beam epitaxy (hereinafter, referred to simply as xe2x80x9cMBExe2x80x9d). Hereinbelow is explained the method with reference to FIGS. 1A to 1D.
First, as illustrated in FIG. 1A, there is formed an Nxe2x88x92 epitaxial layer 2 over an N-type silicon substrate 1. The Nxe2x88x92 epitaxial layer 2 has a thickness ranging from 0.8 to 1.3 xcexcm, and a resistivity ranging from 0.5 to 1.0 xcexa9-cm. Then, the Nxe2x88x92 epitaxial layer 2 is thermally oxidized to thereby form a silicon dioxide film 3 having a thickness of about 100 nm. Then, a part of the silicon dioxide film 3 is removed by photolithography and anisotropic etching to thereby form a base region. Then, silicon and boron are evaporated in an apparatus for carrying out molecular beam epitaxy (hereinafter, referred to simply as xe2x80x9cMBE apparatusxe2x80x9d) which provides about 10xe2x88x928 Torr vacuum to thereby form a P-type layer 4 on the Nxe2x88x92 epitaxial layer 2 at 650xc2x0 C. of growth temperature. The P-type layer 4 has a thickness in the range of 30 to 50 nm, and a carrier concentration on the order of 1018 cmxe2x88x923. Hereinbelow, an layer formed by means of the MBE apparatus, including the P-type layer 4, is referred to as xe2x80x9can MBE layerxe2x80x9d.
Then, silicon and boron are evaporated again in the MBE apparatus to thereby form a Pxe2x88x92 MBE layer 5 over the P-type MBE layer 4 at 650xc2x0 C. of growth temperature. The Pxe2x88x92 MBE layer 5 has a thickness in the range of 5 to 20 nm. The Pxe2x88x92 MBE layer 5 functions as a buffer layer for maintaining both crystallinity at an interface between an emitter and a base and p-n junction in well condition. Thereafter, polysilicon having grown on the silicon dioxide film 3 are removed by means of photolithography and anisotropic etching such as CF4 gas etching.
Then, as illustrated in FIG. 1B, a silicon dioxide film 6 and further a silicon nitride film 7 are formed on the Pxe2x88x92 MBE layer 5 and the silicon dioxide film 3 by chemical vapor deposition (CVD). The silicon dioxide film 6 and the silicon nitride film 7 both have a thickness of about 100 nm. Then, a photoresist 8 is deposited over the silicon nitride film 7, and patterned by photolithography, followed by anisotropic etching to thereby open an emitter region E.
Then, as illustrated in FIG. 1C, silicon and antimony are evaporated in the MBE apparatus to thereby deposit heavily doped amorphous silicon on the silicon substrate 1 at room temperature, followed by solid phase epitaxy at growth temperature of 730xc2x0 C. to thereby form an N+ MBE layer 9 having a thickness in the range of 100 to 200 nm. Then, photolithography and subsequently anisotropic etching such as (CF4+O2) gas etching are carried out to the N+ MBE layer 9 to thereby form an emitter contact 9a. 
The thus obtained emitter contact 9a composed of the N+ MBE layer 9 has been already sufficiently activated. Thus, it is no longer necessary to carry out thermal annealing at high temperature above growth temperature, resulting in that impurities depth profile is scarcely varied, and that it is possible to obtain desired characteristics by controlling thickness of base and emitter and/or carrier concentration.
Thereafter, the photoresist 8 is patterned by photolithography and anisotropically etched to thereby open a base contact B.
Then, as illustrated in FIG. 1D, a titanium (Ti)/platinum (Pt) layer 10 is deposited all over a resultant by vacuum evaporation. A gold layer 11 is deposited on the Ti/Pt layer 10, and then patterned by photolithography. The Ti/Pt layer 10 is anisotropically etched using the patterned gold layer 11 as a mask, to thereby form electrodes of base and emitter of a silicon bipolar transistor.
The above mentioned conventional method has an advantage that an emitter region almost free of crystal defects can be obtained without carrying out thermal annealing at high temperature for activation, because the thin base layer 4 is grown by MBE, and further the N+ MBE layer 9 is grown through solid phase epitaxy process by means of the MBE apparatus. To the contrary, the above mentioned conventional method has many shortcomings.
First, the emitter region is insufficiently shallow in depth, because the emitter region is established only through annealing in solid phase epitaxy.
Secondly, since a diffusion coefficient of boron in the base layer is greater than a diffusion coefficient of antimony in an emitter, a p-n junction interfacial plane between an emitter and a base is almost equal to an epi-poly interfacial plane established through the solid phase epitaxy. As a result, it is impossible to obtain sufficient crystallinity, which causes a base leakage current to be increased, thereby DC characteristic being deteriorated at a low current. As one of evidences for such deterioration, FIG. 2 shows Gummel plots for a transistor fabricated in accordance with the above mentioned conventional method. It is understood in view of the two curves Ic and IB in FIG. 2 that a base current IB is greater than a collector current Ic in the range where a current is small, resulting in that the forward current gain linearity is deteriorated.
Thirdly, a rapid thermal annealing (RTA) apparatus may be used in the conventional method to carry out implantation for forming a shallow emitter region. However, annealing is carried out in so short period of time that temperature in a wafer is not uniformized. As a result, there is generated dispersion in characteristics, which lowers a production yield.
Ion implantation and thermal diffusion, which have been widely used, have a shortcoming that they make the implantation depth so deep that crystal defects are increased, resulting in that it is necessary to carry out thermal annealing at high temperature for activation. In addition, those prior methods have another shortcoming that a silicon wafer has to be taken out of an MBE apparatus each time when ion implantation is to be carried out.
A report No. 27a-T-9 by the title of xe2x80x9cB and Sb Heavy Doping for Si-MBExe2x80x9d in the 51st Applied Physical Society lecture meeting, Vol. 1, pp 239, Autumn 1990, has indicated a problem that it is impossible in conventional methods of fabricating a bipolar transistor to have steep impurities depth profile, because base and emitter are formed by ion implantation and thermal treatment at high temperature such as annealing. Recently, Si-MBE has been applied to formation of a thin base layer for establishing steep impurities depth profile at ambient temperature. However, technique for heavily doping B and Sb is not established yet. Thus, the results of the experiments are reported about activation rate, crystallinity, and dependency on azimuth of substrate planes during B and Sb are being heavily doped.
It is an object of the present invention to provide a semiconductor device and a method of fabricating the same which are capable of forming an emitter region which are shallow, but sufficiently uniform in impurities concentration with the result of no necessity of thermal annealing at high temperature after the formation of a base layer, prevention of degradation of crystallinity, and prevention of variation of impurities depth profile.
In one aspect, there is provided a method of fabricating a semiconductor device, including the steps of (a) forming a first molecular beam epitaxy layer on a semiconductor substrate, (b) implanting impurities into the first molecular beam epitaxy layer, and (c) forming a second molecular beam epitaxy layer on the first molecular beam epitaxy layer.
It is preferable that the second molecular beam epitaxy layer is formed only on a portion of the first molecular beam epitaxy layer into which the impurities have been implanted. The first molecular beam epitaxy layer may be designed to have an opposite conductivity to that of the semiconductor substrate, and the second molecular beam epitaxy layer may have the same conductivity as that of the semiconductor substrate.
There is further provided a method of fabricating a semiconductor device, including the steps of (a) forming a first conductivity type epitaxial layer on a second conductivity type semiconductor substrate, (b) implanting second conductivity type impurities into at least a part of the first conductivity type epitaxial layer, (c) forming a second conductivity type amorphous layer on the part into which the second conductivity type impurities have been implanted, and (d) causing the second conductivity type amorphous layer to grow in solid phase.
There is still further provided a method of fabricating a semiconductor device, including the steps of (a) forming a first conductivity type base region in a second conductivity type collector region by molecular beam epitaxy, (b) forming an emitter region in the base region by implanting second conductivity type impurities into the base region by molecular beam epitaxy, (c) forming a second conductivity type amorphous layer on the emitter region by molecular beam epitaxy, and (d) forming an emitter contact region by causing the second conductivity type amorphous layer to grow in solid phase.
The steps where molecular beam epitaxy is to be accomplished may be carried out in a common apparatus for accomplishing molecular beam epitaxy. The impurities are selected from antimony (Sb), phosphorus (P) and arsenic (As). Impurities implantation is accomplished by application of a voltage directly to the semiconductor substrate during doping.
There is yet further provided a method of fabricating a semiconductor device, including the steps of (a) forming a heavily doped first conductivity type layer buried in a second conductivity type semiconductor substrate, (b) forming a lightly doped first conductivity type epitaxial layer on the heavily doped first conductivity type layer so that the lightly doped first conductivity type epitaxial layer is exposed to a surface of the semiconductor substrate, (c) forming a heavily doped first conductivity type connection layer for connecting the heavily doped first conductivity type layer to a surface of the semiconductor substrate, (d) forming a first molecular beam epitaxy layer on the lightly doped first conductivity type epitaxial layer, the first molecular beam epitaxy layer being of a second conductivity type, (e) implanting first conductivity type impurities into the first molecular beam epitaxy layer to form an impurities implantation layer, and (f) forming a second molecular beam epitaxy layer on both the impurities implantation layer and the connection layer, the second molecular beam epitaxy layer being of a first conductivity type.
For instance, the first molecular beam epitaxy layer may be comprised of a first epitaxial layer and the second molecular beam epitaxy layer may be comprised of an amorphous layer. The method may further include the step of causing the second molecular beam epitaxy layer to grow in solid phase to a second epitaxial layer and a polysilicon layer.
There is further provided a method of fabricating a semiconductor device, including the steps of (a) forming a heavily doped first conductivity type layer buried in a second conductivity type semiconductor substrate, (b) forming a lightly doped first conductivity type epitaxial layer on the heavily doped first conductivity type layer so that the lightly doped first conductivity type epitaxial layer is exposed to a surface of the semiconductor substrate, (c) forming a heavily doped first conductivity type connection layer for connecting the heavily doped first conductivity type layer to a surface of the semiconductor substrate, (d) forming a second conductivity type epitaxial layer on the lightly doped first conductivity type epitaxial layer, (e) implanting first conductivity type impurities into at least a part of the second conductivity type epitaxial layer to form an impurities implantation layer, (f) forming a first conductivity type amorphous layer on both the impurities implantation layer and the connection layer, and (g) causing the first conductivity type amorphous layer to grow in solid phase.
There is further provided a method of fabricating a semiconductor device, including the steps of (a) forming a heavily doped first conductivity type layer buried in a second conductivity type semiconductor substrate, (b) forming a lightly doped first conductivity type epitaxial layer on the heavily doped first conductivity type layer so that the lightly doped first conductivity type epitaxial layer is exposed to a surface of the semiconductor substrate, (c) forming a heavily doped first conductivity type connection layer for connecting the heavily doped first conductivity type layer to a surface of the semiconductor substrate, (d) forming a second conductivity type base region in a first conductivity type collector region on the lightly doped first conductivity type epitaxial layer by molecular beam epitaxy, (e) forming an emitter region in the base region by implanting first conductivity type impurities into the base region by molecular beam epitaxy, (f) forming a first conductivity type amorphous layer on both the emitter region and the connection layer by molecular beam epitaxy, and (g) forming an emitter contact region by causing the first conductivity type amorphous layer to grow in solid phase.
In another aspect, there is provided a semiconductor device including (a) a first conductivity type semiconductor substrate, (b) a first molecular beam epitaxy layer formed on the semiconductor substrate, the first molecular beam epitaxy layer being of a second conductivity type, (c) an impurities implantation layer into which first conductivity type impurities are implanted, formed at a surface of the first molecular beam epitaxy layer, and (d) a second molecular beam epitaxy layer formed on the impurities implantation layer, the second molecular beam epitaxy layer being of a first conductivity type.
The first molecular beam epitaxy layer may be comprised of an epitaxial layer, and the second molecular beam epitaxy layer may be comprised of an amorphous layer. For instance, the impurities are selected from antimony (Sb), phosphorus (Pb) and arsenic (As).
There is further provided a semiconductor device including (a) a first conductivity type semiconductor substrate, (b) a second conductivity type epitaxial layer formed on the semiconductor substrate, (c) an impurities implantation layer comprised of a part of the second conductivity type epitaxial layer into which first conductivity type impurities are implanted, and (d) a first conductivity type amorphous layer formed on the impurities implantation layer.
There is still further provided a semiconductor device including (a) a first conductivity type semiconductor substrate, (b) a second conductivity type base region formed in a first conductivity type collector region of the semiconductor substrate, (c) an emitter region formed in the base region, first conductivity type impurities being implanted in the emitter region, and (d) a first conductivity type amorphous layer formed on the emitter region.
There is yet further provided a semiconductor device including (a) a first conductivity type semiconductor substrate, (b) a heavily doped second conductivity type layer buried in the semiconductor substrate, (c) a lightly doped second conductivity type epitaxial layer formed on the heavily doped second conductivity type layer so that the lightly doped second conductivity type epitaxial layer is exposed to a surface of the semiconductor substrate, (d) a heavily doped second conductivity type connection layer for connecting the heavily doped second conductivity type layer to a surface of the semiconductor substrate, (e) a first molecular beam epitaxy layer formed on the lightly doped second conductivity type epitaxial layer, the first molecular beam epitaxy layer being of a first conductivity type, (f) an impurities implantation layer formed partially at a surface of the first molecular beam epitaxy layer, second conductivity type impurities being implanted into the impurities implantation layer, and (g) a second molecular beam epitaxy layer formed on both the impurities implantation layer and the connection layer, the second molecular beam epitaxy layer being of a second conductivity type.
There is further provided a semiconductor device including (a) a first conductivity type semiconductor substrate, (b) a heavily doped second conductivity type layer buried in the semiconductor substrate, (c) a lightly doped second conductivity type epitaxial layer formed on the heavily doped second conductivity type layer so that the lightly doped second conductivity type epitaxial layer is exposed to a surface of the semiconductor substrate, (d) a heavily doped second conductivity type connection layer for connecting the heavily doped second conductivity type layer to a surface of the semiconductor substrate, (e) a first conductivity type epitaxial layer formed on the lightly doped second conductivity type epitaxial layer, (f) an impurities implantation layer formed partially at a surface of the first molecular beam epitaxy layer, second conductivity type impurities being implanted into the impurities implantation layer, and (g) a second conductivity type amorphous layer formed on both the impurities implantation layer and the connection layer.
There is further provided a semiconductor device including (a) a first conductivity type semiconductor substrate, (b) a heavily doped second conductivity type layer buried in the semiconductor substrate, (c) a lightly doped second conductivity type epitaxial layer formed on the heavily doped second conductivity type layer so that the lightly doped second conductivity type epitaxial layer is exposed to a surface of the semiconductor substrate, (d) a heavily doped second conductivity type connection layer for connecting the heavily doped second conductivity type layer to a surface of the semiconductor substrate, (e) a first conductivity type base region formed in a second conductivity type collector region on the lightly doped second conductivity type epitaxial layer, (f) an emitter region formed in the base region, second conductivity type impurities being implanted into the emitter region, and (g) a second conductivity type amorphous layer formed on both the emitter region and the connection layer.
In accordance with the above mentioned present invention, it is possible to establish not only a base region but also an emitter region in ambient temperature growth by means of an MBE apparatus. Herein, the emitter region can have a shallow depth and a uniform, sufficient impurities content by implanting impurities such as antimony (Sb) into a region with a substrate being DC-biased in an MBE apparatus. Thus, it is no longer necessary to carry out thermal treatment at high temperature after the formation of a base region, resulting in prevention of degradation of crystallinity and prevention of changes in impurities depth profile. In addition, since a p-n junction interfacial plane is formed in a base epitaxial layer, it is possible to obtain better crystallinity with the result of improvement in DC characteristic.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.